Digital logic circuits associated with a memory storage unit can record the transfer of data, commands, or any other information (referred to as “data packets”) with one or more other devices. Data transfer rates can differ between inserting data packets into a memory storage unit and extracting data packets from the memory storage unit.
A control circuit associated with managing data packet insertion and extraction into and out of a memory storage unit can use write and read pointers to address memory storage unit locations. The write pointer increments and points to a subsequent address location of the memory storage unit after each data packet insertion into the memory storage unit. The read pointer similarly increments and points to a subsequent address location of the memory storage unit after each data packet extraction from the memory storage unit. The control circuit compares values of the read and write pointers to track the occupancy of the memory storage unit. Based on the comparison, the control circuit can generate a signal such as a “queue is empty” signal or a “queue is full” signal to indicate whether to continue with a data packet insertion or extraction operation. If the queue is full, the data packet insertion operation by an associated circuit will stop its write operation/data packet insertion. Similarly, if the queue is empty, the associated circuit will stop the read operation/data packet extraction.
The implementation of the control circuit can limit the data rate at which insertions and extractions of data packets can operate. For conventional first in, first out (FIFO) queues, which can have a larger “depth” of the memory storage unit, the sizes of the read and write pointers and comparators in the control circuit can increase proportionally. With the increase in comparator size, the insertion and extraction data rates can be even further reduced. This decreases the operating frequency and throughput of the memory storage unit.